Integrated circuits and/or packages include a plurality of traces for coupling different components together. The chip package bondwires (or onchip or on-board traces) usually has a large inductance. At high frequencies, this large inductance will cause a large RF swing. Furthermore, the large inductance will make the matching wideband applications more difficult.
The conventional way to reduce the inductance of the traces is to parallel multiple bondwires/traces. In this traditional approach, the magnetic coupling factor K has a negative effect on reducing the parallel bondwires/traces inductance. FIG. 1 illustrates the conventional technique to reduce the bondwire/trace inductance. L1-L4 are the chip bondwires, on-chip layout trace or board traces. In the case that L1-L4 are bondwires, P1 and P2 are connected to bondpads on die and P3 and P4 are connected to package pins. In the case that L1-L4 are differential traces on chip or on board, P1 and P2 are differential inputs and P3 and P4 are differential outputs. The conventional way to reduce the inductance is to parallel L1 and L2 (or L3 and L4) to make the effective inductance from P1 to P3 (or P2 to P4) smaller.
Let L1=L2=L3=L4=L, and inductance coupling factor is K. If coupling factor K=0, the effective inductance from P1 to P3 (or P2 to P4) Lpp=L1*L2/9L2+L2)=L/2. If K is not 0, the magnetic fields of the bondwires/traces will strengthen each other and the Lpp>L/2. Accordingly, the larger K is, the larger the Lpp. So the reduction from parallel bondwire approach does necessarily reduce the inductance.
Therefore the traditional method in some instances sometimes does not reduce the inductance. The larger K is, the larger the inductance. Accordingly, what is needed is a system and method to overcome the above-identified issues. The present invention addresses such a need.